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" white electronic designs "# $% the 128mbyte (1gb) ddr sdram is a high-speed cmos, dynamic random-access, memory using 5 chips containing 268,435,456 bits. each chip is internally configured as a quad-bank dram. each of the chip?s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. the 128 mb ddr sdram uses a double data rate architec- ture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128mb ddr sdram effectively consists of a single 2 n -bit wide, one-clock-cycle data tansfer at the internal dram core and two corresponding n -bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a high frequency = 200, 250, 266mhz package: 219 plastic ball grid array (pbga), 32 x 25mm 2.5v 0.2v core power supply 2.5v i/o (sstl_2 compatible) differential clock inputs (clk and clk) commands entered on each positive clk edge internal pipelined double-data-rate (ddr) architecture; two data accesses per clock cycle programmable burst length: 2,4 or 8 bidirectional data strobe (dqs) transmitted/received with data, i.e., source-synchronous data capture (one per byte) dqs edge-aligned with data for reads; center-aligned with data for writes dll to align dq and dqs transitions with clk four internal banks for concurrent operation two data mask (dm) pins for masking write data programmable iol/ioh option auto precharge option auto refresh and self refresh modes commercial, industrial and military temperature ranges organized as 16m x 72 weight: wedpnd16m72s-xbx - 2.5 grams typical 40% space savings reduced part count reduced i/o count 34% i/o reduction reduced trace lengths for lower parasitic capacitance suitable for hi-reliability applications laminate interposer for optimum tce match upgradeable to 32m x 72 density (contact factory for information) * this data sheet describes a product that is not fully qualified or characterized and is subject to change without notice. 25 32 66 tsop 66 tsop 66 tsop 66 tsop 66 tsop 11.9 11.9 11.9 11.9 11.9 22.3 monolithic solution actual size wedpnd16m72s-xbx s a v i n g s area i/o count 5 x 265mm 2 = 1328mm 2 5 x 66 pins = 330 pins 800mm 2 40% 219 balls 34% wedpnd16m72s-xbx white electronic designs & '() white electronic designs note: dnu = do not use; to be left unconnected for future upgrades. nc = not connected internally. 1 2345678910111213141516 a b c d e f g h j k l m n p r t dq 1 dq 3 dq 6 dq 7 cas0 cs 0 v ss v ss clk3 nc dq 56 dq 57 dq 60 dq 62 vss v ss dq 30 dq 28 dq 25 dq 24 clk 1 cke1 v cc v cc cs2 cas2 dq 39 dq 38 dq 35 dq 33 v cc dq 0 dq 2 dq 4 dq 5 dqml0 we0 ras0 v ss v ss cke3 clk3 dqmh3 dq 58 dq 59 dq 61 dq 63 dq 31 dq 29 dq 27 dq 26 nc dqmh1 clk1 v cc q v cc q ras2 we2 dqml2 dq 37 dq 36 dq 34 dq 32 dq 14 dq 12 dq 10 dq 8 v cc v cc v cc v cc v cc v cc v cc v cc dq 55 dq 53 dq 51 dq 49 dq 17 dq 19 dq 21 dq 23 v ss v ss v ss vss v ss v ss v ss v ss dq 40 dq 42 dq 44 dq 46 dq 15 dq 13 dq 11 dq 9 dqmh0 clk 0 cke0 v cc q v cc q cs3 cas3 we3 dq 54 dq 52 dq 50 dq 48 dq 16 dq 18 dq 20 dq 22 dqml1 we1 cs 1 v ss v ss cke2 clk 2 dqmh2 dq 41 dq 43 dq 45 dq 47 v ss v ss v cc v cc q dqsh3 dqsl3 clk0 v ss v ss dqsl4 ras3 dqml3 dqsh4 v ss v cc v cc q v cc q v cc v ss v ss vref ras1 cas1 v cc v cc clk2 dqsl2 cs4 dqsh2 v cc v ss v ss a 9 a 0 a 2 a12 dqsh0 dqmh4 dq73 dq75 dq77 dq79 a 8 a 1 a 3 dnu dqsl1 we4 dq70 dq68 dq66 dq64 a 10 a 7 a 5 dnu ba 0 clk4 dq72 dq74 dq76 dq78 a 11 a 6 a 4 dnu ba 1 cas4 dq71 dq69 dq67 dq65 v ss v ss v cc v ccq dqsl0 cke4 clk4 v ss v cc v cc q v cc q v cc v ss v ss dqsh1 ras4 dqml4 v cc vss v ss ! " white electronic designs a 0-12 a 0-12 ba 0-1 ba 0-1 clk 0 clk cas dq 0 dq 15 cke 0 cke cs 0 cs dqml 0 dqml dqmh 0 dqmh ras 1 we 1 cas 1 dq 0 dq 15 we u1 ras a 0-12 ba 0-1 clk 1 clk cas dq 16 dq 31 ras 0 we 0 cas 0 dq 0 dq 15 we u0 ras cke 1 cke cs 1 cs dqml 1 dqml dqmh 1 dqmh ras 2 we 2 cas 2 dq 0 dq 15 we u2 ras a 0-12 ba 0-1 clk 2 clk cas dq 32 dq 47 cke 2 cke cs 2 cs dqml 2 dqml dqmh 2 dqmh ras 3 we 3 cas 3 dq 0 dq 15 we u3 ras a 0-12 ba 0-1 clk 3 clk cas dq 48 dq 63 cke 3 cke cs 3 cs dqsl 3 dqsl dqsh 3 dqsh ras 4 we 4 cas 4 dq 0 dq 15 we u4 ras a 0-12 ba 0-1 clk 4 clk cas dq 64 dq 79 cke 4 cke cs 4 cs dqsl 4 dqsl dqsh 4 dqsh y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = clk 4 clk v ref clk 3 clk v ref dqsl 2 dqsl dqsh 2 dqsh v ref dqsl 1 dqsl dqsh 1 dqsh v ref dqsl 0 dqsl dqsh 0 dqsh v ref clk 2 clk clk 1 clk clk 0 clk v ref dqml 3 dqml dqmh 3 dqmh dqml 4 dqmh 4 dqml dqmh & '() white electronic designs read and write accesses to the ddr sdram are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac- tive command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information cover- ing device initialization, register definition, command de- scriptions and device operation. ddr sdrams must be powered up and initialized in a pre- defined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to v cc and v ccq simultaneously, and then to v ref (and to the system v tt ). v tt must be applied after v ccq to avoid device latch-up, which may cause permanent dam- age to the device. v ref can be applied any time after v ccq but is expected to be nominally coincident with v tt . except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input but will detect an lvcmos low level after v cc is applied. maintaining an lvcmos low level on cke during power-up is required to ensure that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read ac- cess). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a load mode reg- ister command should be issued for the extended mode register (ba1 low and ba0 high) to enable the dll, fol- lowed by another load mode register command to the mode register (ba0/ba1 both low) to reset the dll and to program the operating parameters. two-hundred clock cycles are required between the dll reset and any read command. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed (t rfc must be satisfied.) additionally, a load mode register command for the mode register with the reset dll bit deactivated (i.e., to program operating param- eters without resetting the dll) is required. following these requirements, the ddr sdram is ready for normal operation. the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the strobe transmitted by the ddr sdram during reads and by the memory contoller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. each chip has two data strobes, one for the lower byte and one for the upper byte. the 128mb ddr sdram operates from a differential clock (clk and clk); the crossing of clk going high and clk going low will be referred to as the positive edge of clk. commands (address and control signals) are registered at every positive edge of clk. input data is registered on both edges of dqs, and output data is refer- enced to both edges of dqs, as well as to both edges of clk. read and write accesses to the ddr sdram are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac- tive command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power- saving power-down mode. ! " white electronic designs -200 75 100 -250 100 125 -266 100 133 selection of a burst length, a burst type, a cas latency, and an operating mode, as shown in figure 3. the mode regis- ter is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. (except for bit a8 which is self clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent opera- tion. violating either of these requirements will result in un- specified operation. mode register bits a0-a2 specify the burst length, a3 speci- fies the type of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a12 specify the operating mode. read and write accesses to the ddr sdram are burst ori- ented, with the burst length being programmable, as shown in figure 3. the burst length determines the maximum num- ber of column locations that can be accessed for a given read or write command. burst lengths of 2, 4 or 8 loca- tions are available for both the sequential and the inter- leaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of col- umns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two; by a2-ai when the burst length is set to four (where ai is the most significant column address for a given configuration); and by a3-ai when the burst length is set to eight. the remaining (least significant) ad- dress bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2 or 2.5 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . table 2 below indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 1. the normal operating mode is selected by issuing a mode register set command with bits a7-a12 each set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. although not required, jedec specifications recommend when a load mode reg- ister command is issued to reset the dll, it should always be followed by a load mode register command to se- lect normal operating mode. all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. & '() white electronic designs the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, and qfc. these functions are controlled via the bits shown in figure 5. the extended mode register is programmed via the load mode register command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode register (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subse- quent operation. violating either of these requirements could result in unspecified operation. !" "# "$%& '( )% *+ ',--+!!+! $".$%# !" +%&". ** +!! / 2 0 0-1 0-1 1 1-0 1-0 0 / 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 / 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 12++3 +%"$#( 12+%"+ (+#4+* notes: 1. for a burst length of two, a1-ai select two-data-element block; a0 selects the starting column within the block. 2. for a burst length of four, a2-ai select four-data-element block; a0-1 select the starting column within the block. 3. for a burst length of eight, a3-ai select eight-data-element block; a0-2 select the starting column within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. m3 = 0 2 4 8 reserved reserved reserved m3 = 1 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 0 valid valid 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a 10 a 11 * m14 and m13 (ba0 and ba1 must be "0, 0" to select the base mode register (vs. the extended mode register). 0* 0* ba 0 ba 1 reserved reserved reserved reserved m9 m10 m11 0 0 0 10 0 0 0 -- - - - - a 12 m12 0 0 - ! " white electronic designs the deselect function (cs high) prevents new commands from being executed by the ddr sdram. the sdram is effectively deselected. operations already in progress are not affected. the no operation (nop) command is used to perform a nop to the selected ddr sdram (cs is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. the mode registers are loaded via inputs a0-12. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. command read nop nop nop cl = 2.5 don't care transitioning data dq dqs t0 t1 t2 t2n t3 t3n command read nop nop nop cl = 2 dq dqs clk clk t0 t1 t2 t2n t3 t3n burst length = 4 in the cases shown shown with nominal tac and nominal tdsdq data clk clk the normal full drive strength for all outputs are specified to be sstl2, class ii. the ddr sdram supports an option for reduced drive. this option is intended for the support of the lighter load and/or point-to-point environments. the selection of the reduced drive strength will alter the dqs and dqss from sstl2, class ii drive strength to a reduced drive strength, which is approximately 54 percent of the sstl2, class ii drive strength. the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon return- ing to normal operation after having disabled the dll for the purpose of debug or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur be- fore a read command can be issued. 5 the truth table provides a quick reference of available commands. this is followed by a written description of each command. dll enable disable dll ds a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 extended mode register (ex) address bus operating mode a 10 a 11 1 1 0 1 ba 0 ba 1 qfc e0 0 1 drive strength normal reduced e1 0 1 qfc function disabled reserved e2 2 0 - operating mode reserved reserved e2, e1, e0 valid - e12 0 - e10 0 - e9 0 - e8 0 - e7 0 - e6 0 - e5 0 - e4 0 - e3 0 - a 12 e11 0 - 1. e14 and e13 must be "0, 1" to select the extended mode register (vs. the base mode register) 2. the qfe function is not supported. & '() white electronic designs the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the d/qs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the correspond- ing data will be written to memory; if the dqm signal is regis- tered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. notes: 1. cke is high for all commands shown except self refresh. 2. a0-12 define the op-code to be written to the selected mode register. ba0, ba1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. a0-12 provide row address, and ba0, ba1 provide bank address. 4. a0-8 provide column address; a10 high enables the auto precharge feature (non persistent), while a10 low disables the auto p recharge feature; ba0, ba1 provide bank address. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. deselect and nop are functionally interchangeable. 10. used to mask write data; provided coincident with the corresponding data. the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address pro- vided on inputs a0-12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 se- lects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto deselect (nop) (9) h x x x x no operation (nop) (9) l h h h x active (select bank and activate row) ( 3) l l h h bank/row read (select bank and column, and start read burst) (4) l h l h bank/col write (select bank and column, and start write burst) (4) l h l l bank/col burst terminate (8) l h h l x precharge (deactivate row in bank or banks) ( 5) l l h l code auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x load mode register (2) llll op-code ! write enable (10) l v alid write inhibit (10) h x precharge is not selected, the row will remain open for subsequent accesses. ! " white electronic designs the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is is- sued. except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing pa- rameters. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge is a feature which performs the same indi- vidual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or dis- abled for each individual read or write command. the device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. this ?earliest valid stage? is determined as if an explicit precharge command was is- sued at the earliest possible time, without violating t ras (min). the user must not issue another command to the same bank until the precharge time (t rp ) is completed. this is deter- mined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min). the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated. the open page which the read burst was terminated from remains open. auto refresh is used during normal operation of the ddr sdram and is analogous to cas-before-ras (cbr) re- fresh in conventional drams. this command is nonpersis- tent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh control- ler. this makes the address bits ?don?t care? during an auto refresh command. each ddr sdram requires auto re- fresh cycles at an average interval of 7.8125 s (maximum). to allow for improved efficiency in scheduling and switch- ing between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given ddr sdram, mean- ing that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 x 7.8125 s (70.3 s). this maximum absolute interval is to allow future support for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing excessive drift in t ac between updates. although not a jedec requirement, to provide for future func- tionality features, cke must be active (high) during the auto refresh period. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram re- tains data without external clocking. the self refresh com- mand is initiated like an auto refresh command except cke is disabled (low). the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input sig- nals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr , because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll re- quirements is to apply nops for 200 clock cycles before applying any other command. * self refresh available in commercial and industrial temperatures only. & '() white electronic designs / # #)+"+ 6 '%*$"$'% 1)7'( 88 // %$"! operating current: one bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs i dd0 600 575 ma changing once per clock cyle; address and control inputs changing once every two clock cycles; (22, 48) operating current: one bank; active-read-precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i dd1 825 775 ma iout = 0ma; address and control inputs changing once per clock cycle (22, 48) precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); i dd2p 20 20 ma cke = low; (23, 32, 50) idle standby current: cs = high; all banks idle; t ck = t ck (min); cke = high; address and other control i dd2f 200 200 ma inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm (51) active power-down standby current: one bank active; power-down mode; t ck = t ck (min); i dd3p 150 125 ma cke = low (23, 32, 50) active standby current: cs = high; cke = high; one bank; active-precharge; t rc = t ras (max); i dd3n 225 200 ma t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle (22) operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs i dd4r 1250 1075 ma changing once per clock cycle; t ck = t ck (min); i out = 0ma (22, 48) operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs i dd4w 1250 950 ma changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle (22) auto refresh current t rc = t rc (min) (27, 50) i dd5 1225 1075 ma t rc = 7.8125s (27, 50) i dd5a 30 30 ma self refresh current: cke 0.2v standard (11) i dd6 20 20 ma operating current: four bank interleaving reads (bl=4) with auto precharge, t rc =t rc (min); t ck = t ck (min); i dd7 2000 1875 ma address and control inputs change only during active read or write commands. (22, 49) # #)+"+ 6 '%*$"$'% 1)7'( %$"! $% #9 supply voltage v cc 2.3 2.7 v i/o supply voltage v ccq 2.3 2.7 v input high voltage: logic 1; all inputs (21) v ih v ref - 0.04 v ref + 0.04 v input low voltage: logic 0; all inputs (21) v il -0.3 v ref - 0.15 v input leakage current: any input 0v v in v cc (all other pins not under test = 0v) i i -2 2 a input leakage address current (all other pins not under test = 0v) i i -10 10 a output leakage current: i/os are disabled; 0v v out v cc i oz -5 5 a output levels: full drive option - x4, x8, x16 high current (v out = v ccq - 0.373v, minimum v ref, minimum v tt )i oh -16.8 - ma low current (v out = 0.373v, maximum v ref , maximum v tt )i ol 16.8 - ma output levels: reduced drive option - x16 only high current (v out = v ccq - 0.763v, minimum v ref, minimum v tt )i ohr -9 - ma low current (v out = 0.763v, maximum v ref , maximum v tt )i olr 9-ma i/o reference voltage v ref 0.49 x v ccq 0.51 x v ccq v i/o termination voltage v tt v ref - 0.04 v ref + 0.04 v 5 # #)+"+ %$" voltage on v cc , v ccq supply relative to vss -1 to 3.6 v voltage on i/o pins relative to vss -1 to 3.6 v operating temperature t a (mil) -55 to +125 c operating temperature t a (ind) -40 to +85 c storage temperature, plastic -55 to +150 c note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress ra ting only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification i s not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. # #)+"+ 1)7'( #9 %$" input capacitance: clk c i1 8pf addresses, ba 0-1 input capacitance ca 30 pf input capacitance: all other input-only pins c i2 9pf input/output capacitance: i/os c io 12 pf ! " white electronic designs # #)+"+ 1)7'( $% #9 $% #9 $% #9 %$"! access window of dqs from clk/clk t ac -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns clk high-level width (30) t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clk low-level width (30) t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock cycle time cl = 2.5 (45, 52) t ck (2.5) 7.5 13 8 13 10 13 ns cl = 2 (45, 52) t ck (2) 10 13 10 13 13 15 ns dq and dm input hold time relative to dqs (26, 31) t dh 0.5 0.6 0.6 ns dq and dm input setup time relative to dqs (26, 31) t ds 0.5 0.6 0.6 ns dq and dm input pulse width (for each input) (31) t dipw 1.75 2 2 ns access window of dqs from clk/clk t dqsck -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access (25, 26) t dqsq 0.5 0.6 0.6 ns write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to clk rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from clk rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period (34) t hp t ch ,t cl t ch ,t cl t ch ,t cl ns data-out high-impedance window from clk/clk (18, 42) t hz +0.75 +0.8 +0.8 ns data-out low-impedance window from clk/clk (18, 43) t lz -0.75 -0.8 -0.8 ns address and control input hold time (fast slew rate) (14) t ih f .90 1.1 1.1 ns address and control input setup time (fast slew rate) (14) t is f .90 1.1 1.1 ns address and control input hold time (slow slew rate) (14) t ih s 1 1.1 1.1 ns address and control input setup time (slow slew rate) (14) t is s 1 1.1 1.1 ns load mode register command cycle time t mrd 15 16 16 ns dq-dqs hold, dqs to first dq to go non-valid, per access (25, 26) t qh t hp -t qhs t hp -t qhs t hp -t qhs ns data hold skew factor t qhs 0.75 1 1 ns active to precharge command (35) t ras 40 120,000 40 120,000 40 120,000 ns active to read with auto precharge command (46) t rap 20 20 20 ns active to active/auto refresh command period t rc 65 70 70 ns auto refresh command period (50) t rfc 75 80 80 ns active to read or write delay t rcd 20 20 20 ns precharge command period t rp 20 20 20 ns dqs read preamble (42) t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 15 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time (20, 21) t wpres 000ns dqs write postamble (19) t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 111t ck data valid output window (25) na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns refresh to refresh command interval (23) t refc 70.3 70.3 70.3 s average periodic refresh interval (23) t refi 7.8 7.8 7.8 s terminating voltage delay to vdd t vtd 000ns exit self refresh to non-read command t xsnr 75 80 80 ns exit self refresh to read command t xsrd 200 200 200 t ck & '() white electronic designs notes: 1. all voltages referenced to v ss . 2. tests for ac timing, i cc , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i cc tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for clk/clk), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ccq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (noncommon mode) on v ref may not exceed 2 percent of the dc value. thus, from v ccq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. v id is the magnitude of the difference between the input level on clk and the input level on clk. 9. the value of v ix and v mp are expected to equal v ccq /2 of the transmitting device and must track variations in the dc level of the same. 10. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time with the outputs open. 11. enables on-chip refresh and address counters. 12. i cc specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. this parameter is sampled. v cc = +2.5v 0.2v, v ccq = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out (dc) = v ccq /2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. command/address input slew rate = 0.5v/ns. for 266 mhz with slew rates 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 15. the clk/clk input reference level (for timing referenced to clk/clk) is the point at which clk and clk cross; the input reference level for signals other than clk/clk is v ref. 16. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v ccq is recognized as low. 17. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt. 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 22. min (t rc or t rfc) for i cc measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i cc measurements is the largest multiple of t ck that meets the maximum absolute value for t ras . 23. the refresh period 64ms. this equates to an average refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other specifications - thp (t ck /2), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. referenced to each output group: ldqs with dq0-dq7; and udqs with dq8-dq15. 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period (t rfc [min]) else cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: 160 140 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) i out (ma) maximum nominal high nominal low minimum 50 ? reference point 30pf output (v out ) v tt 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 v ccq - v out (v) i out (ma) maximum nominal high nominal low minimum ! " white electronic designs a) sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. clk and clk input slew rate must be 1v/ns ( 2v/ns differentially). 31. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 32. v cc must not vary more than 4% if cke is not active while any bank is active. 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device clk and clk inputs, collectively during bank active. 35. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the internal precharge command being issued. 36. any positive glitch must be less than 1/3 of the clock and not more than +400mv or 2.9 volts, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2 volts, whichever is more positive. 37. normal output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure a. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure a. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure b. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure b. e) the full variation in the ratio of the maximum to minimum pull-up and pull- down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 volt. 38. reduced output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure c. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure c. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure d. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure d. e) the full variation in the ratio of the maximum to minimum pull-up and pull- down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 v, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 v. 39. the voltage levels used are derived from a minimum v cc level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. v ih overshoot: v ih (max) = v ccq +1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. v cc and v ccq must track each other. 42. this maximum value is derived from the referenced test load. in practice, the values obtained in a typical terminated design may reflect up to 310ps less for t hz (max) and the last dvw. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 43. for slew rates greater than 1v/ns the (lz) transition will start about 310ps earlier. 44. during initialization, v ccq , v tt, and v ref must be equal to or less than v cc + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v cc / v ccq are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 45. the current part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not reflect this option. 46. reserved for future use. 47. reserved for future use. 48. random addressing changing 50% of data changing at every transfer. 49. random addressing changing 100% of data changing at every transfer. 50. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until tref later. 51. idd2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. idd2q is similar to idd2f except idd2q specifies the address and control inputs to remain stable. although idd2f, idd2n, and idd2q are similar, idd2f is ?worst case.? 52. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) i out (ma) maximum nominal high nominal low minimum 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0.0 0.2 0.4 0.6 0.8 1.0 v ccq - v out (v) i out (ma) maximum nominal high nominal low minimum & '() white electronic designs all linear dimensions are millimeters and parenthetically in inches 32.32 (1.272) max 12345678910111213141516 t r p n m l k j h g f e d c b a 25.25 (0.994) max 0.60 (0.024) 0.10 (0.004) 2.20 (0.087) max 19.05 (0.750) nom 1.27/2 1.27/2 1.27 (0.050) bsc 19.05 (0.750) nom 219 x ? 0.835 ! :089; < '=+ 22(1 200 = 200mhz 250 = 250mhz 266 = 266mhz > b = 219 plastic ball grid array (pbga) < > m = military 55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c junction to ambient theta ja 13.3 c/w 1 (no airflow) junction to ball theta jb 9.9 c/w 1 junction to case (top) theta jc 3.8 c/w 1 " refer to an #0001 at www.whiteedc.com in the application notes section for modeling conditions. ! " white electronic designs !"# $#%! !&$'$ " $'# () !"#$ %& " ' '()* !"# +$ ,'%& % - " ' ( '% ' % - . !"##/#+#$ %& % - " '0+% 1+234 " '+% 134 ". '+% 1+234 "/ '+% 134 "+ '+% 1+234 " '+% 134 " ' "0 ' "5 '% 1+234 " '0+% 134 " ) % )& |
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